Orange
This board was an off-site rogue design done almost exclusively by Heath Computer Engineering Director Larry Plummer. The Orange was a pre-cursor to the production Z-100 and was intended to include such features as voice synthesis and BSR X-10 control. It was a prototype of a "home computer" that would challenge the Apple II and TRS-80 machines. This board was basically a proof of concept for an 8088 hardware design and used as a software development platform by Gregg Chandler, Jim Tittsler and others. The primary OS was CP/M.
Z100
The Z100 was a dual CPU machine featuring both an 8085 and an 8088 CPU. The machine featured very advanced (for the day) bit mapped video that allowed up to 640 x 512 pixels of 8 color graphics. The Z100 was in development when the IBM PC was released, and was a much more powerful machine. The original design team for the Z100 was Mike Hakeem (manager), Chuck Krause (team lead), Babu Rajaram (CPU Architecture and Video), Mike Gorbutt, Randy VanderHeyden (firmware) Steve Parker (firmware), Mark Nicol (technician) and Ralph Rumph (technician).
Z 100 (Z Machine) Concept Plan written by Larry Plummer, May 1980
Z100 project staffing, June 1980
Z 100 (Z Machine) Development Plan written by Carl Goy
Z150
This was the first IBM compatible machine that ZDS produced. The design team was headed by Chuck Krause.
Z159
This was a second generation IBM PC compatible designed by Babu Rajaram.
Python/Mongoose/Mamba
The Mongoose project was started around the same time that the Compaq 386/20 was announced. To achieve high performance and low costs, the decision was made to design custom ASIC solutions for both cache control and bus/memory control. The design team for the cache controller ASIC was primarily Tony Olson and Jimmy Smith. The design team for the bus/memory controller ASIC was Bill McAuliffe, Gordon Helm and Mark Nicol. Richard Ball, Terry O'Brien and Terry Hussey also were involved in the ASIC development and verification. The ASIC design environment was schematic capture using Daisy workstations. The main PCB was designed by Mark Nicol.
The primary system board features were:
CPU: Intel 80386
Clock Speed: 20 MHz (Python)
25 MHz (Mongoose)
33 MHz (Mamba)Coprocessor Options: Intel 80387
Weitek WTL 3167Memory, Standard: 2 Megabytes (1M for Python) Max. (1M SIMM)
8 Megabytes Max. (4M SIMM)
32 Megabytes Max. (16M SIMM)Max Addressable: 64 Megabytes
Cache: 16Kb x 32 direct mapped (optional)
4Kb x 32 direct mapped (standard)
2Kb x 32 direct mapped (optional)Cache hit rate: 95 per cent or greater
Write Queue: 16 locations deep x 66 bits wide
System Expansion: 3 PC-AT compatible slots4 32-bit ZDS proprietary slots
Circuit Board: 6 layers, SMT and thru-hole
Viper
The Viper project was a 486 based design using ZDS custom ASICs. The primary design team was Tony Olson and Jimmy Smith.
Piranha
The Piranha project was basically an extension of the Mongoose to the new EISA bus. The Mongoose memory/bus controller was used as a memory controller only, with bus control functionality handled by the Intel 82357 and 82358 EISA controller. The main PCB was designed by Mark Nicol.
CPU: Intel 80386
Clock Speed: 33 MHz
Coprocessor Option: Intel 80387
Weitek WTL 3167Memory, Standard: 4 Megabytes
Max.(1M SIMM): 8 Megabytes
Max.(4M SIMM): 32 Megabytes
Max Addressable: 4 GigabytesCache: 16K x 32 direct mapped (optional)
4K x 32 direct mapped (standard)
2K x 32 direct mapped (optional)Cache hit rate: 95 per cent or greater
Write Queue: 16 locations deep x 66 bits wide
System Expansion: 8 EISA compatible slots
Circuit Board: 8 layers, SMT and thru-hole
Aurora
The Aurora design was an EISA based system employing modular design. The main board was based on the Intel 82358 EISA controller and the 82359 memory controller. The 82359 used an asynchronous and programmable CPU interface allowing various types of CPUs to be used. Programmable state trackers (PSTs), implemented in PLDs provided the correct timing for each CPU. 80386SX and 80386DX CPU modules were available with and without external cache modules. The main board provided proprietary expansion slots for SCSI, Ethernet and WAM (windows accelerator module) boards. The chassis and cabinet was codenamed NDL (new design language) and the styling was designed by Frog Design. The design team for the Aurora project was Tom Robinson (team lead), Mark Nicol (main board), Todd Witkowski and Vince Messina (486 CPU modules w/PST), Bernie Suzor (386 CPU modules), Jerry Jacobs (WAM module), Dale Joachim (SCSI), Dave Miller (Ethernet) and Mike Krau (BIOS).
An ISA based machine (Orion) was also available in the same chassis, designed by Jim Smith.
The main features of the system electronics were as follows:
- Modular CPU architecture allowing 80386SX @20MHz to 80386DX2 @ 66MHz with/without cache
- Modular backplane allows either 2 or 4 EISA bus slots for expansion boards
- Memory capacity of 4M (minimum) to 128M maximum with 8 banks of 1, 4, or 16M SIMMs
- Field upgradeable BIOS in 128K FLASH ROM
- Extended VGA video with 1024 x 768 resolution @ 16 colors
- Ethernet LAN adapter
- SCSI bus interface
- IDE drive interface
- Floppy drive controller supporting 4M media
- Serial I/O port
- Parallel I/O port
- PS/2 compatible Mouse port
- PS/2 compatible Keyboard connector